Aaron G. Lucas

1916 Harmony Dr
Fort Collins, C0 80525
303-921-4492
aglucas@yahoo.com

Objective

To find a rewarding position that will utilize my skills, inspire my imagination, and satisfy my desire to create new products and improve on existing products.

Education	Master of Science, Electrical Engineering: Solid State Microelectronics
	The University of Texas at Austin: May 1999 Thesis: How processing effects, oxynitride gate dielectric performance in MOSFETS.

Bachelor of Science, Electrical Engineering: Materials and Devices

The University of Texas at Austin: May 1994

Skills

System Design - Used System on a Chip design methodology.  Strong foundation in design for reuse concepts. Direct work with SAS, SATA, PATA, AHB, and SERDES operation. Used many different tools (ncv, modelsim, prime-time, debussy, amplify, design compiler, and others) to complete chip designs.  Verified designs using a combination of Quickbench, Verilog, Assembly, C++ programs, formal verification tools and linting tools.

Device Processing - Developed 0.5 um transistor process for testing ultra-thin oxynitrides (designed the mask set and process flow). Used TSuprem4 and Medici software to facilitate development. Produced and tested transistors. Studied transistor characteristics (gm, ueff, and hot electron effects). Strong knowledge of semiconductor processing techniques.

Computer - Programming languages: VHDL,Verilog, Assembly, C ++, Java, perl, unix scripting, and Quickbench Rave. 

Experience

01/01 - Present	Circuit Designer LSI Logic, Fort Collins Product Development
	Designed clock structure for multi-clock domain chip. Involved determining the best way to perform glitch less control of all clocks. Development of asyncronous Intel 196 micro interface. Involved a non-clocked 196 micro interface that transferred data to and from registers, ram interfaces, and an external DDR buffer. All blocks in chip did not conform to a standard method, thus communication between designers was very important. Development of AHB syncronous interface. Involved replacing 196 interface with a new interface with features such as bust reads and writes. Designed this interface to have a caching system, special log FIFO’s for transferring data to an external DDR part, and maintain high performance. Fiber Channel phy level protocol upgrade from 2 gig to 4 gig fiber channel, upgraded existing phy to work with new SERDES. Worked on implementation into a dual fiber channel, SAS device. Protocol development, coding and testing for existing PATA to SATA bridge chip. During work at LSI, verification, sythesis and static timing of designs was performed. Large portions of work involved describing circuits to other Engineers to achive the desired design via the LSI process. Worked with analog Engineers to develop process independent delay elements for precision interface timing. All designs involved testing using various test methodology, such as stand alone module test and system verification. Testing of other Engineers designs was also done.
11/99 - 01/01	Design/ Verification Engineer for Motorola, MMD division - Austin, TX
	Verification of Micro-controllers.  Work involved writing tests that exercised the specified function of modules in the micro-controller.  Worked on many different designs including system clock generators, port interfaces, interrupt modules, and system integration modules.  Worked with team members to solve problems in chip specifications and designs.
08/97 - 06/99	Graduate Research Assistant, Microelectronics Research Center  The University of Texas at Austin
	Focused on the effects of process conditions and environment on breakdown characteristics and transistor performance. Designed MOS transistor flow and testing statigies.  Supporting Professor Dr. Jack Lee
06/96 - 08/97	Research Assistant, Microelectronics Research Center  The University of Texas at Austin
	Qualification of equipment including: furnaces, lithographic tools, wet hoods, and sputtering tools. Fabricated CMOS capacitors and studied their electrical characteristics to determine quality of the equipment. Installed incoming equipment (plasma etch, wet etch, and probe stations).  Upgraded FAB from 4” to 6” wafers. Supporting Professor Dr. Al Tasch
11/94 - 05/96	Field Service Engineer, Novellus Systems - Austin, TX
	Customer support of dielectric and tungsten CVD equipment. Work involved system reliability, process reliability, and system installations.
06/91 - 06/94 08/94 - 11/94	Research Assistant, Microelectronics Research Center The University of Texas at Austin
	Maintained equipment (PECVD, dry etch, wet etch, furnaces, sputtering systems, and probe stations). Fabricated parts and specialty tools. Supported graduate students in there work. Supporting Professor Dr. Al Tasch

Related Courses	Cadence Basic Verilog, VHDL Design for Synthesis, Summit RTL Coding Style for Synythis, Serial Attached ATA protocol, Serial Attached SCSI protocol, VLSI Design and Simulation, Digital System Design, CMOS Analog Circuit Design, Digital Signal Processing, Microelectronic Fabrication, Microelectronic Packaging, MOS Integration, SubMicron Device Physics and Techniques
Employability Status	US Citizen / Permanent Resident